The development of ever more powerful computing systems has for decades driven the most rapid technology advance in the human history. Currently, billions of digital microprocessors facilitate our daily life and empower our anticipations for a better future on earth. However, modern demands such as big data analysis, artificial intelligence, or energy efficient computing cannot be capably fulfilled with the current aging computing technology. For more than forty years, improvement in computer performance was derived by scaling down of CMOS transistors. This performance improvement slowed down after hitting the heat and memory walls, and approaching its physical scaling limits by the mid of 2020's. Therefore, there is an imperative need to shift to new technologies, at both the architecture and the device levels. Recently, resistive memory, based on the concept of memristors, have attracted attention for being a promising candidate for future computing needs due to their fast operating speed, low power, high endurance, and very high density.
Along its history, digital computers passed through four different generations, namely, Cathode Ray Tubes (CRTs), transistors, Integrated Circuit (ICs) and microprocessors. Here it is clearly noted that technology advance at the device level always marked the transition from each generation to the other. We believe that the recent development in resistive memory devices is the key for the fifth computer generation. For instance, the high-density memristor crossbar structure is wildly considered as a promising candidate for nonvolatile storage and Random Access Memory (RAM) systems. Furthermore, analog resistive devices have been shown to be well suited for bio-inspired analog computing systems and can significantly outperforms classical digital computing in many “soft” computing applications where the task is complex but approximate solutions are tolerated such as data classification, recognition, and analysis. At the other end of the spectrum, many trials have also been presented in the literature to perform accurate digital computations using binary resistive memory devices. In these cases, systems based on these emerging devices are normally studied as accelerators for a subset of specialized tasks, e.g. data storage, neuromorphic computing, and arithmetic analysis, and each task uses different physical device properties, circuits, and system organization to achieve the specialized goals. While utilizing these subsystems in a traditional computing platform is expected to achieve improved performance, particularly for the targeted tasks, a general computing system that can handle different tasks in a changing environment in fast and energy-efficient manner still remain to be desired.
In this disclosure, a common physical block that can store data and process it in-place in an analog or digital fashion is presented. Utilizing binary resistive crossbar, crossbar-based binary neural networks, arithmetic tree reduction, and in-situ data migration are presented. This enables the proposed field programmable crossbar array (FPCA) computing system to achieve three outstanding features using the same physical system, without hardware reconfigurations. Firstly, the ability to process any arbitrary workload in its optimal computing domain (Digital or Analog). Secondly, the natively modular design of the system allows a high degree of scalability and the ability to tailor fit different workload. Finally, it merges processing and memory together at the lowest physical level to achieve maximal efficiency and minimal data migration. Such a combination enables high-performance computing for different tasks with a much smaller energy budget compared to classical Von Neumann architectures to perform natively scalable, reconfigurable (i.e. software-defined) and energy-efficient computing.
This section provides background information related to the present disclosure which is not necessarily prior art.